Master Silicon Design with Vplay
LearnVLSI is your gateway to hands-on semiconductor engineering. Powered by Vplay—a unique, one-of-a-kind browser environment that unites a 90-Day Gamified Verilog Practice Course with a complete RTL-to-GDSII Physical Design Foundry.
The Product — Vplay
One Unified Platform. From First Verilog Line to Final GDSII.
No Linux setup, no multi-gigabyte PDK downloads, and no expensive licenses. Vplay runs entirely in your browser with two powerful modes.
1. 90-Day Verilog Practice Arena
A gamified, hands-on HDL coding arena built to take you from basic logic gates to synthesizable processor design with instant automated testbench grading.
- Write Verilog directly in an interactive browser editor
- Instant verification against pre-built hardware testbenches
- Structured 90-day daily streak & progression system
- One-click push from verified RTL into physical silicon synthesis
2. Complete RTL-to-GDSII Foundry
Turn your verified Verilog code into a manufacturable chip layout using the open-source OpenLane & SkyWater 130nm toolchain in the cloud.
- Real Yosys logic synthesis & OpenROAD floorplanning
- Interactive Power Delivery Network (PDN) & placement tuning
- Clock Tree Synthesis (CTS) & TritonRoute metal routing
- Built-in AI assistant to debug DRC & PDN pitch errors
90-Day Practice Curriculum
Learn Verilog by Solving Real Hardware Challenges
Stop passively watching tutorials. Practice daily for 90 days with curated problems and automated testbench verification.
Digital Logic & Combinational
Build a rock-solid foundation in gate-level modeling, dataflow assignments, and modular arithmetic blocks.
Sequential Circuits & FSMs
Master clocked logic, state machines, counters, and hardware communication interfaces.
Memory, Datapaths & RISC-V
Design complex, synthesizable microarchitectures ready to be pushed through Vplay's RTL-to-GDSII flow.
Physical Design Flow
The 7-Track RTL-to-GDSII Pipeline
Step through every stage of physical chip design and inspect your layout visually in the browser.
RTL-to-GDSII Express
Execute a complete push-button compilation from Verilog to a physical GDSII mask layout.
Logic Synthesis (Yosys)
Translate RTL into a standard-cell netlist and analyze gate counts, area, and timing.
Floorplan & PDN Sizing
Configure core utilization, die area, and power delivery network stripes without pitch violations.
Placement & Legalization
Place standard cells across the core and resolve routing congestion and density hotspots.
Clock Tree Synthesis
Build balanced clock distribution networks to minimize skew and insertion delay.
Routing & DRC Sign-off
Run TritonRoute across Sky130 metal layers and verify clean DRC and LVS reports.
Custom Silicon Foundry
Take any module from your 90-Day Verilog Practice—or upload your own custom RTL—and synthesize it into a real Sky130 layout.
The Developer
Engineered for the VLSI Community
Nirmalya Sinha
Nirmalya is a hardware engineer specializing in RTL architecture, FPGA acceleration, and open-source ASIC physical design flows (with research experience at IIT-BHU and RRU). He built LearnVLSI and Vplay to remove the steep infrastructure barriers of EDA tools—giving every student and engineer a fast, accessible browser environment to practice Verilog for 90 days and take real designs from RTL to GDSII.
Ready to write Verilog and build real silicon?
Start your 90-Day Verilog Practice or launch the 7-Track RTL-to-GDSII Foundry inside your browser.
Launch Vplay Now →